From 1ec3d6c4a529c07a97bb6b2b6b57047f57ad31c9 Mon Sep 17 00:00:00 2001 From: Vasile Vilvoiu Date: Mon, 9 Nov 2020 17:07:29 +0200 Subject: Enable B soldermask layer; add BOM --- kicad/catahack.pro | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'kicad/catahack.pro') diff --git a/kicad/catahack.pro b/kicad/catahack.pro index 1a38296..fd7b540 100644 --- a/kicad/catahack.pro +++ b/kicad/catahack.pro @@ -1,4 +1,4 @@ -update=11/5/2020 7:43:21 PM +update=11/7/2020 10:04:44 PM version=1 last_client=kicad [general] @@ -12,6 +12,16 @@ NetIExt=net version=1 LibDir= [eeschema/libraries] +[schematic_editor] +version=1 +PageLayoutDescrFile= +PlotDirectoryName=./ +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName=Pcbnew +SpiceAjustPassiveValues=0 +LabSize=50 +ERC_TestSimilarLabels=1 [pcbnew] version=1 PageLayoutDescrFile= @@ -211,7 +221,7 @@ Enabled=1 [pcbnew/Layer.F.SilkS] Enabled=1 [pcbnew/Layer.B.Mask] -Enabled=0 +Enabled=1 [pcbnew/Layer.F.Mask] Enabled=1 [pcbnew/Layer.Dwgs.User] @@ -248,13 +258,3 @@ uViaDrill=0.1 dPairWidth=0.2 dPairGap=0.25 dPairViaGap=0.25 -[schematic_editor] -version=1 -PageLayoutDescrFile= -PlotDirectoryName=./ -SubpartIdSeparator=0 -SubpartFirstId=65 -NetFmtName=Pcbnew -SpiceAjustPassiveValues=0 -LabSize=50 -ERC_TestSimilarLabels=1 -- cgit v1.2.3