From 1ec3d6c4a529c07a97bb6b2b6b57047f57ad31c9 Mon Sep 17 00:00:00 2001 From: Vasile Vilvoiu Date: Mon, 9 Nov 2020 17:07:29 +0200 Subject: Enable B soldermask layer; add BOM --- bom/ibom.html | 3428 ++++++++++++++++++++++++++++++++++++++++++++++ kicad/catahack.kicad_pcb | 33 +- kicad/catahack.pro | 24 +- 3 files changed, 3457 insertions(+), 28 deletions(-) create mode 100644 bom/ibom.html diff --git a/bom/ibom.html b/bom/ibom.html new file mode 100644 index 0000000..a9288ed --- /dev/null +++ b/bom/ibom.html @@ -0,0 +1,3428 @@ + + + + + + + Interactive BOM for KiCAD + + + + + +
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Board statsFrontBackTotal
Components~~~
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SMD pads~~~
TH pads~
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+ + + diff --git a/kicad/catahack.kicad_pcb b/kicad/catahack.kicad_pcb index 9431e8a..628b94c 100644 --- a/kicad/catahack.kicad_pcb +++ b/kicad/catahack.kicad_pcb @@ -18,20 +18,21 @@ (layers (0 F.Cu signal) - (1 In1.Cu power hide) + (1 In1.Cu power) (2 In2.Cu power hide) (31 B.Cu signal) - (33 F.Adhes user) - (35 F.Paste user) - (36 B.SilkS user) + (33 F.Adhes user hide) + (35 F.Paste user hide) + (36 B.SilkS user hide) (37 F.SilkS user) + (38 B.Mask user) (39 F.Mask user) - (40 Dwgs.User user) - (41 Cmts.User user) - (42 Eco1.User user) - (43 Eco2.User user) + (40 Dwgs.User user hide) + (41 Cmts.User user hide) + (42 Eco1.User user hide) + (43 Eco2.User user hide) (44 Edge.Cuts user) - (45 Margin user) + (45 Margin user hide) (46 B.CrtYd user) (47 F.CrtYd user) (49 F.Fab user hide) @@ -73,7 +74,7 @@ (aux_axis_origin 0 0) (visible_elements 7FFFFFFF) (pcbplotparams - (layerselection 0x01020_ffffffff) + (layerselection 0x010f0_ffffffff) (usegerberextensions false) (usegerberattributes false) (usegerberadvancedattributes false) @@ -7006,7 +7007,7 @@ (segment (start 44.6675 57.15) (end 45.085 57.5675) (width 1) (layer F.Cu) (net 136)) (segment (start 40.259 57.15) (end 44.6675 57.15) (width 1) (layer F.Cu) (net 136)) - (zone (net 59) (net_name PC_AUDIO_GND) (layer In1.Cu) (tstamp 5FA6CE32) (hatch edge 0.508) + (zone (net 59) (net_name PC_AUDIO_GND) (layer In1.Cu) (tstamp 5FA6FF50) (hatch edge 0.508) (connect_pads (clearance 0.508)) (min_thickness 0.254) (fill yes (arc_segments 32) (thermal_gap 0.508) (thermal_bridge_width 0.508)) @@ -7275,7 +7276,7 @@ ) ) ) - (zone (net 4) (net_name XCVR_GND) (layer In1.Cu) (tstamp 5FA6CE2F) (hatch edge 0.508) + (zone (net 4) (net_name XCVR_GND) (layer In1.Cu) (tstamp 5FA6FF4D) (hatch edge 0.508) (connect_pads (clearance 0.508)) (min_thickness 0.254) (fill yes (arc_segments 32) (thermal_gap 0.508) (thermal_bridge_width 0.508)) @@ -7761,7 +7762,7 @@ ) ) ) - (zone (net 2) (net_name GND) (layer In1.Cu) (tstamp 5FA6CE2C) (hatch edge 0.508) + (zone (net 2) (net_name GND) (layer In1.Cu) (tstamp 5FA6FF4A) (hatch edge 0.508) (connect_pads (clearance 0.508)) (min_thickness 0.254) (fill yes (arc_segments 32) (thermal_gap 0.508) (thermal_bridge_width 0.508)) @@ -8042,7 +8043,7 @@ ) ) ) - (zone (net 1) (net_name VCC) (layer In2.Cu) (tstamp 5FA6CE29) (hatch edge 0.508) + (zone (net 1) (net_name VCC) (layer In2.Cu) (tstamp 5FA6FF47) (hatch edge 0.508) (connect_pads (clearance 0.508)) (min_thickness 0.254) (fill yes (arc_segments 32) (thermal_gap 0.508) (thermal_bridge_width 0.508)) @@ -8342,7 +8343,7 @@ ) ) ) - (zone (net 30) (net_name XCVR_5V) (layer In2.Cu) (tstamp 5FA6CE26) (hatch edge 0.508) + (zone (net 30) (net_name XCVR_5V) (layer In2.Cu) (tstamp 5FA6FF44) (hatch edge 0.508) (connect_pads (clearance 0.508)) (min_thickness 0.254) (fill yes (arc_segments 32) (thermal_gap 0.508) (thermal_bridge_width 0.508)) @@ -8597,7 +8598,7 @@ ) ) ) - (zone (net 7) (net_name XCVR_13V8) (layer In2.Cu) (tstamp 5FA6CE23) (hatch edge 0.508) + (zone (net 7) (net_name XCVR_13V8) (layer In2.Cu) (tstamp 5FA6FF41) (hatch edge 0.508) (connect_pads (clearance 0.508)) (min_thickness 0.254) (fill yes (arc_segments 32) (thermal_gap 0.508) (thermal_bridge_width 0.508)) diff --git a/kicad/catahack.pro b/kicad/catahack.pro index 1a38296..fd7b540 100644 --- a/kicad/catahack.pro +++ b/kicad/catahack.pro @@ -1,4 +1,4 @@ -update=11/5/2020 7:43:21 PM +update=11/7/2020 10:04:44 PM version=1 last_client=kicad [general] @@ -12,6 +12,16 @@ NetIExt=net version=1 LibDir= [eeschema/libraries] +[schematic_editor] +version=1 +PageLayoutDescrFile= +PlotDirectoryName=./ +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName=Pcbnew +SpiceAjustPassiveValues=0 +LabSize=50 +ERC_TestSimilarLabels=1 [pcbnew] version=1 PageLayoutDescrFile= @@ -211,7 +221,7 @@ Enabled=1 [pcbnew/Layer.F.SilkS] Enabled=1 [pcbnew/Layer.B.Mask] -Enabled=0 +Enabled=1 [pcbnew/Layer.F.Mask] Enabled=1 [pcbnew/Layer.Dwgs.User] @@ -248,13 +258,3 @@ uViaDrill=0.1 dPairWidth=0.2 dPairGap=0.25 dPairViaGap=0.25 -[schematic_editor] -version=1 -PageLayoutDescrFile= -PlotDirectoryName=./ -SubpartIdSeparator=0 -SubpartFirstId=65 -NetFmtName=Pcbnew -SpiceAjustPassiveValues=0 -LabSize=50 -ERC_TestSimilarLabels=1 -- cgit v1.2.3