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| author | Vasile Vilvoiu <vasi.vilvoiu@gmail.com> | 2020-10-31 20:37:40 +0200 |
|---|---|---|
| committer | Vasile Vilvoiu <vasi.vilvoiu@gmail.com> | 2020-10-31 20:37:40 +0200 |
| commit | 4a69d458120c24bbf534ae1edfc173c6a2f41c48 (patch) | |
| tree | 92952c7694b5cb7e64697124c3fc2e98b2b58535 /kicad/catahack.pro | |
| parent | 2e0350c71473aa1ee7c07b6c114b980b119ee34f (diff) | |
Initial commit.
Diffstat (limited to 'kicad/catahack.pro')
| -rw-r--r-- | kicad/catahack.pro | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/kicad/catahack.pro b/kicad/catahack.pro new file mode 100644 index 0000000..529cd92 --- /dev/null +++ b/kicad/catahack.pro @@ -0,0 +1,43 @@ +update=10/31/2020 6:40:10 PM +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +[schematic_editor] +version=1 +PageLayoutDescrFile= +PlotDirectoryName=./ +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName= +SpiceAjustPassiveValues=0 +LabSize=50 +ERC_TestSimilarLabels=1 |